Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

7.2.2.2.3.1. On-Chip RAM Transaction Configuration

Because all memories are secure when they exit reset, the on-chip RAM Security Control Register block must be configured by a secure master before non-secure or shared memory accesses are allowed.

  1. Configure the base and limit fields of the regionNaddr register, where N denotes the region number.
  2. Enable the non-secure memory region by setting the corresponding regionNenable bit in the enable_set register, where N denotes the region number.