Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

14.4.4. Local Memory Buffer

The NAND flash controller has three local SRAM memory buffers.

  • The write FIFO buffer is a 128 × 32-bit memory (512 total bytes)
  • The read FIFO buffer is a 32 × 32-bit memory (128 total bytes)
  • The ECC buffer is a 96 × 16-bit memory (1536 total bytes)

Each of these memories is protected by ECC, and by interrupts for single and double-bit errors. The ECC block is integrated around a memory wrapper. It provides outputs to notify the system manager when single-bit correctable errors are detected (and corrected) and when double-bit uncorrectable errors are detected. The ECC logic also allows injection of single- and double-bit errors for test purposes. It must be initialized to enable the ECC function.