Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

21.4.5.1. Minimum High and Low Counts

When the I2C controller operates as an I2C master in both transmit and receive transfers, the minimum value that can be programmed in the SCL low count registers is 8 while the minimum value allowed for the SCL high count registers is 6. †

The minimum value of 8 for the low count registers is due to the time required for the I2C controller to drive SDA after a negative edge of SCL. The minimum value of 6 for the high count register is due to the time required for the I2C controller to sample SDA during the high period of SCL. †

The I2C controller adds one cycle to the low count register values in order to generate the low period of the SCL clock.

The I2C controller adds seven cycles to the high count register values in order to generate the high period of the SCL clock. This is due to the following factors: †

  • The digital filtering applied to the SCL line incurs a delay of four l4_sp_clk cycles. This filtering includes metastability removal and a 2-out-of-3 majority vote processing on SDA and SCL edges. †
  • Whenever SCL is driven 1 to 0 by the I2C controller—that is, completing the SCL high time—an internal logic latency of three l4_sp_clk cycles incurs. †

Consequently, the minimum SCL low time of which the I2C controller is capable is nine (9) l4_sp_clk periods (8+1), while the minimum SCL high time is thirteen (13) l4_sp_clk periods (6+1+3+3). †

Note: The ic_fs_spklen register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that is filtered out by the spike suppression logic.†