Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

30.5. Lightweight HPS-to-FPGA AXI Master Interface

The lightweight HPS‑to‑FPGA AXI master interface, h2f_lw_axi_master, is connected to a Mentor Graphics AXI master BFM for simulation with an instance name of h2f_lw_axi_master_inst. Platform Designer (Standard) configures the BFM as shown in the following table. The BFM clock input is connected to h2f_lw_axi_clock clock.

Table 268.  Configuration of Lightweight HPS-to-FPGA AXI Master BFM

Parameter

Value

AXI Address Width

21

AXI Read and Write Data Width

32

AXI ID Width

12

You control and monitor the AXI master BFM by using the BFM API.