Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

3.3.2. PLL Integration

The two PLLs contain exactly the same set of output clocks. PLL0 is intended to be used for the MPU and the NOC clocks. PLL1 is intended to be used as the 250 MHz Ethernet clock reference.

Figure 6. PLL Integration in Clock Manager
Table 13.  PLL Output Clock Characteristics
Output Counter Clock Name Frequency Boot Frequency
C0 mpu_base_clk Up to varies 10 MHz to 200 MHz
C1 noc_base_clk Up to C0/3 10 MHz to 200 MHz
C2 emaca_clk 50 to 250 MHz 10 MHz to 200 MHz
C3 emacb_clk 50 to 250 MHz 10 MHz to 200 MHz
C4 emac_ptp_clk Up to 100 MHz 10 MHz to 200 MHz
C5 gpio_db_clk Up to 200 MHz 10 MHz to 200 MHz
C6 sdmmc_clk Up to 200 MHz 10 MHz to 200 MHz
C7 h2f_user0_clk Up to 400 MHz 10 MHz to 200 MHz
C8 h2f_user1_clk Up to 400 MHz 10 MHz to 200 MHz
7 Frequency depends on device, refer to device datasheet for more information.