Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

6.2. System Manager Block Diagram and System Integration

The system manager connects to the level 4 (L4) bus through a slave interface. The CSRs connect to signals in the FPGA and other HPS modules.

Figure 15. System Manager Block Diagram

The system manager consists of the following:

  • CSRs—Provide memory-mapped access to control signals and status for the following HPS modules:
    • EMACs
    • Debug core
    • SD/MMC controller
    • NAND controller
    • USB controllers
    • DMA controller
    • System interconnect
    • ECC memory interfaces for the following peripherals:
      • USB controllers
      • SD/MMC controller
      • Ethernet MACs
      • DMA controller
      • NAND flash controller
      • On-chip RAM
  • Slave port interface—provides access to system manager CSRs for connected masters.
  • Watchdog debug pause—accepts the debug mode status from the MPU subsystem and pauses the L4 watchdog timers.
  • Reset Manager— system manager receives the reset signals from reset manager.