Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

18.3.3.1. MDIO Interface

The MDIO interface signals are synchronous to l4_mp_clk in all supported modes.

Note: The MDIO interface signals can be routed to both the FPGA and HPS I/O.
Table 180.  PHY MDIO Management Interface

Signal

HPS I/O Pin Name

In/Out

Width

Description

emac_gmii_mdi_i EMACn_MDIO

In

1

Management Data In. The PHY generates this signal to transfer register data during a read operation. This signal is driven synchronously with the gmii_mdc_o clock.

emac_gmii_mdo_o

Out

1

Management Data Out. The EMAC uses this signal to transfer control and data information to the PHY.

emac_gmii_mdo_o_e

Out

1

Management Data Output Enable. This enable signal drives the gmii_mdo_o signal from an external three-state I/O buffer. This signal is asserted whenever valid data is driven on the gmii_mdo_o signal. The active state of this signal is high.

emac_gmii_mdc_o EMACn_MDC

Out

1

Management Data Clock. The EMAC provides timing reference for the gmii_mdi_i and gmii_mdo_o signals on MII through this aperiodic clock. The maximum frequency of this clock is 2.5 MHz. This clock is generated from the application clock through a clock divider.