Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

8.2.1.5. Address Remapping

The system interconnect supports address remapping through the noc_addr_remap_value, noc_addr_remap_set, and noc_addr_remap_clear registers in the system manager. Remapping allows software to control which memory device (on-chip RAM or boot ROM) is accessible at address 0x0. The remap registers can be modified by the MPU and the FPGA-to-HPS bridge.

The following master interfaces are affected by the remap bits:

  • MPU master interface
    • L2 cache master 0 interface
  • Non-MPU master interfaces
    • DMA master interface
    • Master peripheral interfaces
    • Debug Access Port (DAP) master interface
    • FPGA-to-HPS bridge master interface