Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

8.2.9.1. Functional Description of the SDRAM Scheduler

The SDRAM scheduler functions as a multi-port front end (MPFE), scheduling transactions from multiple masters to the SDRAM.

The SDRAM scheduler manages transactions to the memory access regions in the SDRAM. These memory regions are defined by the SDRAM L3 firewalls. The second-stage bootloader is expected to program the scheduler with the correct timings to implement optimal access patterns to the hard memory controller.

The SDRAM scheduler has the following features:

  • Five input connections
    • One 64-bit connection from the MPU
    • One 64-bit connection from the main L3 interconnect
    • Two 128/64/32-bit connections from the FPGA
    • One 64/32-bit connection from the FPGA
  • Single 256-bit connection to the SDRAM L3 adapter
    • Capable of issuing transactions at the memory device line rate
    • Traffic is comprised of aggregate inputs