Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

20.4.4.1. RXD Sample Delay

The SPI master device is capable of delaying the default sample time of the rxd signal in order to increase the maximum achievable frequency on the serial bus.

Round trip routing delays on the sclk_out signal from the master and the rxd signal from the slave can mean that the timing of the rxd signal, as seen by the master, has moved away from the normal sampling time.

Without the RXD sample delay, you must increase the baud rate for the transfer in order to ensure that the setup times on the rxd signal are within range. This reduces the frequency of the serial interface.

Additional logic is included in the SPI master to delay the default sample time of the rxd signal. This additional logic can help to increase the maximum achievable frequency on the serial bus.  †

By writing to the rsd field of the RXD sample delay register (rx_sample_dly), you specify an additional amount of delay applied to the rxd sample. The delay is in number of l4_main_clk clock cycles, with 64 maximum cycles allowed (zero is reserved). If the rsd field is programmed with a value exceeding 64, a zero delay is applied to the rxd sample.

The sample delay logic has a resolution of one l4_main_clk cycle. Software can “train” the serial bus by coding a loop that continually reads from the slave and increments the master's RXD sample delay value until the correct data is received by the master. †

Figure 106. Effects of Round Trip Routing Delays on sclk_out Signal