Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

8.3.4.4. Bandwidth and Saturation

Encoding Bandwidth Values

The QoS bandwidth setting is frequency-dependent. Low-frequency masters require a larger value to achieve the same bandwidth as higher frequency masters.

You can calculate the register value for a bandwidth as follows:

*I_main_QosGenerator_Bandwidth = ( bandwidth / frequency ) * 256

where bandwidth is in MBps and frequency is in MHz.

For example, to configure the FPGA-to-SDRAM 0 QoS generator for a bandwidth of 1000 MBps at 200 MHz, calculate the register value as follows:

fpga2sdram0_axi128_I_main_QosGenerator_Bandwidth = ( 1000 / 200 ) * 256 = 1280.

Encoding Saturation Values

The QoS saturation represents the period of time that the master bandwidth is evaluated. The saturation value represents units of 16 bytes of data transferred. For example a 64-bit master that should have the bandwidth re-evaluated every 100 clock cycles would use a saturation setting of 100 cycles * 8 bytes / 16 bytes =50

The saturation register controls the number of bytes that the initiator can transmit at full speed before the limiter or regulator takes effect. The register encodes the byte count as a multiple of 16 bytes. Therefore you can calculate the register value as follows:

*I_main_QosGenerator_Saturation = nbytes / 16

For example, to let the MPU initiator send 64 bytes at full speed, calculate the register value as follows:

mpu_m1_I_main_QosGenerator_Saturation = 64 / 16 = 4