Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

26.2. HPS I/O Block Diagram and System Integration

The HPS I/O block consists of the following sub-blocks:

  • Dedicated pin multiplexers (MUXes) – MUXes for the dedicated I/O bank
  • Shared pin multiplexers – MUXes for the shared I/O bank
  • FPGA access pin multiplexers – MUXes for HPS peripheral connections to the FPGA fabric
  • Register slave interface – Provides access to control registers, which allow the bootloader to initialize I/O pins and HPS peripheral interfaces at system startup
Figure 153. HPS I/O Block Diagram