Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

18.4.3. System Manager Configuration Interface

The System Manager configures several static EMAC functions as shown in the following table. Software must configure these functions appropriately prior to using the EMAC module. Refer to the Ethernet Programming Model section for more details regarding pertinent System Manager registers.

Table 182.  System Manager Control Settings
Function Description

PHY Select

Select RESET, RGMII, RMII or GMII/MII as the PHY interface. The RESET mode is the default out of reset and configures the EMAC to use an internal clock rather than depending on a PHY to provide and active clock. The RESET mode cannot be used with any PHY, and another setting must be programmed before attempting to communicate with a PHY.

PTP Timestamp Reference Select

This field selects if the Timestamp reference is internally or externally generated. EMAC0 must be set to Internal Timestamp. EMAC0 may be the master to generate the timestamp for EMAC1 and EMAC2. EMAC1 and EMAC2 may be set to either Internal or External.

PTP Timestamp Clock Select

Selects the source of the PTP reference clock between emac_ptp_clk from the Clock Manager or f2s_emac_ptp_ref_clk from the FPGA Fabric. All three EMAC modules must use the same reference clock.

AXI Cache and Protection Settings

Static settings are provided to drive the ARCACHE, AWCACHE, ARPROT, and AWPROT signals for the AXI DMA bus.

FPGA Interface Enable

This field enables logic from the FPGA. This signal is only for safety to prevent spurious inputs from the FPGA before the FPGA is configured.