Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

12.4.4.4.2. Register Interface Tests

You can correct memory errors and test the memory register interface through registers in the ECC Controller.

Single-Bit Error Test

The following registers can be used to test and correct memory:
  • ECC_Addrbus: Holds the address of the memory and ECC data.
  • ECC_RData3bus through ECC_RData0bus: Holds memory data from a read access.
  • ECC_WData3bus through ECC_WData0bus: Holds the data to be written to memory.
  • ECC_RDataecc1bus and ECC_RDataecc0bus: Holds the ECC data from a read access.
  • ECC_WDataecc1bus and ECC_WDataecc0bus: Holds the ECC data to be written to memory.
  • ECC_accctrl: Configures the access as a read or a write and enables memory and ECC data overwrites.
  • ECC_startacc: Initiates the register interface access of memory data or ECC data.
This sequence tests the single-bit error detection and correction in the ECC decoder.
  1. Enable the ECC by setting the ECC_EN bit in the CTRL register.
  2. Set the Data Override (DATAOVR) bit in the ECC_accctrl register.
  3. Write data to an address location in memory using a normal memory write. Expect the correct ECC data to be generated.
  4. Write a data value that has one bit altered in the ECC_WData3bus through ECC_WData0bus registers and write the address of the memory location in the ECC_Addrbus.
  5. Configure the ECC_accctrl register to a write and set the ENBUSA bit of the ECC_startacc register to initiate the write. If the memory is dual-ported, an ENBUSB bit could optionally be enabled depending on the port access.
  6. Read the same memory location using a normal memory read access. Expect a single-bit error to be logged but the data read to be correct. Refer to the "Error Logging" section for more details about identifying errors.

Double-Bit Error Test

This sequence tests the double-bit error detection in the ECC decoder.

  1. Enable the ECC by setting the ECC_EN bit in the CTRL register.
  2. Set the Data override (DATAOVR) bit in the ECC_accctrl register.
  3. Write data to an address location in memory using a normal memory write. Expect the correct ECC data to be generated.
  4. Write a data value that has two bits altered in the ECC_WData3bus through ECC_WData0bus registers and write the address of the memory location in the ECC_Addrbus.
  5. Configure the ECC_accctrl register to a write and set the ENBUSA bit of the ECC_startacc register to initiate the write. If the memory is dual-ported, an ENBUSB bit could optionally be enabled depending on the port access.
  6. Read the same memory location using a normal memory read access. Expect a double-bit error to be logged with no data correction. Refer to the "Error Logging" section for more details about identifying errors.