Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

27. Introduction to the HPS Component

The hard processor system (HPS) component is a wrapper that interfaces logic in the user design to the HPS hard logic, simulation models, BFMs, and software handoff files. It instantiates the HPS hard logic in the user design; and enables other soft components to interface with the HPS hard logic. The HPS component itself has a small footprint in the FPGA fabric, because its only purpose is to enable soft logic to connect to the extensive hard logic in the HPS. You can connect soft logic to the HPS.

After the soft logic is connected to the HPS, Platform Designer (Standard) ensures the following features:

  • Interoperability by adapting Avalon® Memory-Mapped (Avalon-MM) interfaces to AXI*
  • Handle data width mismatches
  • Clock domain transfer crossing

This allows you to integrate IP from Intel, 3rd party IP cores, and custom IP cores to the HPS without having to create integration logic.

For a description of the HPS and its integration into the system on a chip (SoC), refer to the  Intel Intel® Arria® 10 Device Datasheet.

For a description of the HPS system architecture and features, refer to the "Introduction to the Hard Processor" and the CoreSight* Debug and Trace chapters in the Intel Intel® Arria® 10 Device Datasheet.

For more information about instantiating the HPS component, refer to the Instantiating the HPS Component chapter in the Hard Processor System Technical Reference Manual.

For more information about the HPS component interfaces, refer to the HPS Component Interfaces chapter in the Hard Processor System Technical Reference Manual.

For more information about simulating the HPS component, refer to the Simulating the HPS Component chapter in the Hard Processor System Technical Reference Manual.