Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

15.3. SD/MMC Controller Signal Description

The following tables show the SD/MMC controller signals that are routed to the FPGA and the HPS I/O.
Note: For more information on how each of the signals are routed to the FPGA and HPS I/O pins, refer to the HPS Component Interfaces chapter.
Table 137.  SD/MMC Controller Interface I/O Pins (Routed to the HPS I/O)

Signal

Width

Direction

Description

Default Value for Inputs Recommended Tie-off
sdmmc_cclk_out

1

Out

Clock from controller to the card

sdmmc_cmd_i

1

In

Card command

1'b1 Pull-up
sdmmc_cmd_o 1 Out
sdmmc_cmd_oe   Out
sdmmc_pwr_ena_o

1

Out

External device power enable

sdmmc_data_i

8

In

Card data

8'b11111111 Pull-up
sdmmc_data_o 8 Out
sdmmc_data_oe 1 Out 0
Table 138.  SD/MMC Controller Interface I/O Pins (Routed to the FPGA I/O)

Signal

Width

Direction

Description

Default Value for Inputs Recommended Tie-off
sdmmc_cdn_i 1 In Card detect signal - active low 1'b0 Pull-down
sdmmc_wp_i 1 In Card write protect signal - active high 1'b0 Pull-down
sdmmc_vs_o 1 Out Voltage switching between 3.3V and 1.8V 0
sdmmc_rstn_o 1 Out Card reset signal used in MMC mode
sdmmc_card_intn_i 1 In Card interrupt signal - active low 1'b1 Pull-up