Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

8.2.1.3. MPU Address Space

The MPU address space is 4 GB and applies to MPU masters.

Addresses generated by the MPU are decoded in three ways:

  • By default, MPU accesses to locations between 0x100000 (1 MB) to 0xC0000000 (3 GB) are made to the SDRAM controller.
  • Addresses in the SCU and L2 register region (0xFFFFC000 to 0xFFFFFFFF) are the SCU and L2 bus.
  • Accesses to all other locations are made to the L3 interconnect.

The MPU L2 cache controller contains a master connected to the main L3 interconnect and a master connected to the SDRAM L3 interconnect.

The system interconnect noc_addr_remap_value, noc_addr_remap_set, and noc_addr_remap_clear registers, in the System Manager, determine if the address space starting at address 0x0 is mapped to the on-chip RAM (256 KB) or the ROM (128 KB). The ROM is mapped to address 0x0 on reset.

The MPU address space contains the following regions:

Table 46.  MPU Default Address Space Regions
Description Condition

Base Address

End Address

Size

Boot ROM remap0 clear, remap1 clear 10

0x00000000

0x0001FFFF

128 KB
SDRAM window Always visible

0x00100000

0xBFFFFFFF 3071 MB

(3 GB – 1 MB)

HPS-to-FPGA Always visible 0xC0000000 0xFBFFFFFF 960 MB

(1 GB – 64 MB)

System trace macrocell Always visible 0xFC000000 0xFFEFFFFF 48 KB
Debug access port Always visible 0xFF000000 0xFF1FFFFF 2 MB
Lightweight HPS-to-FPGA Always visible 0xFF200000 0xFF3FFFFF 2 MB
Peripherals Always visible 0xFF800000 0xFFDFFFFF 6 MB
On-chip RAM Always visible 0xFFE00000 0xFFFE3FFF 256 KB
Boot ROM Always visible 0xFFFC0000 0xFFFDFFFF 128 KB
SCU and L2 registers Always visible 0xFFFFC000 0xFFFFFFFF 16 KB

Boot Region

The boot region is 1 MB, based at address 0x0. The boot region is visible to the MPU only when the L2 address filter start register is set to 0x100000. The L3 noc_addr_remap_value control register determines if the boot region is mapped to the on-chip RAM or the boot ROM.

The boot region is mapped to the boot ROM on reset. Only the lowest 128 KB of the boot region are legal addresses because the boot ROM is only 128 KB.

When the L2 address filter start register is set to 0, SDRAM obscures access to the boot region. This technique can be used to gain access to the lowest SDRAM addresses after booting completes.

SDRAM Window Region

The SDRAM window region provides access to a large, configurable portion of the 4 GB SDRAM address space. The address filtering start and end registers in the L2 cache controller define the SDRAM window boundaries.

The boundaries are megabyte-aligned. Addresses within the boundaries route to the SDRAM master, while addresses outside the boundaries route to the system interconnect master.

Addresses in the SDRAM window match addresses in the SDRAM address space. Thus, the lowest 1 MB of the SDRAM is not visible to the MPU unless the L2 address filter start register is set to 0.

HPS-to-FPGA Slaves Region

The HPS-to-FPGA slaves region provides access to slaves in the FPGA fabric through the HPS-to-FPGA bridge. Software can move the top of the SDRAM window by writing to the L2 address filter end register. If higher addresses are made available in the SDRAM window, part of the FPGA slaves region might be inaccessible to the MPU.

Lightweight HPS-to-FPGA Slaves Region

The lightweight FPGA slaves provide access to slaves in the FPGA fabric through the lightweight HPS-to-FPGA bridge.

Peripherals Region

The peripherals region is near the top of the address space. The peripherals region includes slaves connected to the L3 interconnect and L4 buses.

On-Chip RAM Region

The on-chip RAM is always mapped near the top of the address space, independent of the boot region contents.

Boot ROM Region

The boot ROM is always mapped near the top of the address space, independent of the boot region contents.

SCU and L2 Registers Region

The SCU and L2 registers region provides access to internally-decoded MPU registers (SCU and L2).

10 For details about the noc_addr_remap_value register, refer to "Memory Map Remap Bits".