Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

A.4.4.3.3. Quad SPI Controller CSEL Settings

Table 321.  QSPI Controller Clock Options Based on CSEL and HPS_CLK Fuse Settings
Note: The osc1_clk signal is sourced from the external oscillator input, HPS_CLK1.

CSEL [3:0] Fuse Values

HPS CLK Fuse Value

Required Input Clock Range

Controller clock Controller Clock Frequency (l4_main_clock) Baud Rate Divisor

External Device Clock (Divided down reference clock)

Default Flash Read Instruction PLL Status

0x0-0x1 and 0x3-0xF

1 60-200 MHz (Secure Bypass) cb_intosc_hs_clk 60-200 MHz 16 3.75-12 MHz READ

Bypassed

0x2 1 30-100 MHz (Secure PLL) cb_intosc_ls_clk*4 120-400 MHz 8 15-50 MHz FAST_READ

Locked

0x1 0 10-50 MHz (Untouched PLL) osc1_clk 10-50 MHz 4 2.50-12.5 MHz READ

Untouched

0x0-0x6, 0xF 0 10-50 MHz (PLL Bypass) osc1_clk 10-50 MHz 4 2.50-12.5 MHz READ

Bypassed

0x7

0 10-15 MHz osc1_clk*26.75 266.67-400 MHz 8 33.33-50 MHz FAST_READ

Locked

0x8

0 15-20 MHz osc1_clk*20 300-400 MHz 8 37.50-50 MHz FAST_READ

Locked

0x9 0 20-25 MHz osc1_clk*16 320-400 MHz 8 40-50 MHz FAST_READ

Locked

0xA 0 25-30 MHz osc1_clk*13.33 333.33-400 MHz 8 41.66-50 MHz FAST_READ

Locked

0xB 0 30-35 MHz osc1_clk*11.42 42.85-50 MHz 8 42.85-50 MHz FAST_READ

Locked

0xC 0 35-40 MHz osc1_clk*10 350-400 MHz 8 43.75-50 MHz FAST_READ

Locked

0xD 0 40-45 MHz osc1_clk*8.88 355.55-400 MHz 8 44.45-50 MHz FAST_READ

Locked

0xE 0 45-50 MHz osc1_clk*3 360-400 MHz 8 45-50 MHz FAST_READ

Locked