Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

4.1.1. Reset Controller

In secure mode, all signals are synchronous to boot_clk. In non-secure mode, all signals are synchronous to the clock signal osc1_clk which is sourced from the external oscillator input pin, HPS_CLK1. The following table lists the reset sources external to the HPS.

Table 18.  HPS External Reset Sources

Source

Description

f2h_cold_rst_req_n

Cold reset request from FPGA fabric (active low)

f2h_warm_rst_req_n

Warm reset request from FPGA fabric (active low)

f2h_dbg_rst_req_n

Debug reset request from FPGA fabric (active low)

load_csr_filt

Cold-only reset from FPGA control block (CB)

nPOR

Power-on reset pin (active low)

nRST

Warm reset pin (active low)

Table 19.  HPS External Reset Outputs

Source

Description

h2f_cold_rst_n

Cold-only reset to FPGA fabric (active low)

h2f_rst_n

Cold or warm reset to FPGA fabric (active low)

h2f_dbg_rst_n

Debug reset (dbg_rst_n) to FPGA fabric (active low)

The reset controller performs the following functions:

  • Accepts reset requests from the FPGA control block (CB), FPGA fabric, modules in the HPS, and reset pins
  • Generates an individual reset signal for each module instance for all modules in the HPS
  • Provides reset handshaking signals to support system reset behavior

The reset controller generates module reset signals from external reset requests and internal reset requests. External reset requests originate from sources external to the reset manager. Internal reset requests originate from control registers in the reset manager.

The reset controller supports the following cold reset requests:

  • Security manager reset
  • Cold reset request pin (nPOR)
  • FPGA fabric
  • FPGA CB
  • Software cold reset request bit (swcoldrstreq) of the control register (ctrl)

The reset controller supports the following warm reset requests:

  • Warm reset request pin (nRST)
  • FPGA fabric
  • Software warm reset request bit (swwarmrstreq) of the ctrl register
  • MPU watchdog reset requests for CPU0 and CPU1
  • System watchdog timer 0 and 1 reset requests

The reset controller supports the following debug reset requests:

  • CDBGRSTREQ from DAP
  • FPGA fabric
Figure 10. Reset Controller Signals