Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

8.2.9.2.1.1. ECC Write Behavior

When data is written to SDRAM, the SDRAM controller generates an ECC based on the write data and the write address.

If the write transaction is a partial write (less than 64 bits wide), the SDRAM adapter implements it as a read-modify-write (RMW) sequence, as follows:

  • Reads existing data from the specified address
  • Combine the write data with the existing data
  • Generates the ECC based on the combined data and the write address
  • Writes the combined data back to the write address