Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

9.3.4.2. HPS-to-FPGA Bridge Clocks and Resets

The master interface into the FPGA fabric operates in the hps2fpga_clk clock domain. The clock is provided by user logic. The slave interface of the bridge in the HPS logic operates in the l3_main_clk clock domain. The bridge provides clock crossing logic that allows the logic in the FPGA to operate in any clock domain, asynchronous from the HPS.

The HPS-to-FPGA bridge has one reset signal, hps2fpga_bridge_rst_n. The reset manager drives this signal to the HPS-to-FPGA bridge on a cold or warm reset.

Note: Make sure that all transactions on the bridge are completed before shutting down and resetting the bridge. If the system is unable to meet this recommendation, the Arria 10 SoC device has a built-in timeout that can be enabled to force all outstanding transactions on the bridge to complete. The NoC timeout is enabled by setting the en bit in the System Manager’s noc_timeout register. Ensure that the bridge operates at 100 MHz or faster when the NoC timeout is enabled. If the bridge is operating below 100 MHz, the timeout does not occur.