Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

21.5.2.2. Dynamic IC_TAR or IC_10BITADDR_MASTER Update

The I2C controller supports dynamic updating of the IC_TAR (bits 9:0) and IC_10BITADDR_MASTER (bit 12) bit fields of the IC_TAR register. You can dynamically write to the IC_TAR register provided the following conditions are met: †

  • The I2C controller is not enabled (IC_ENABLE=0); †
  • The I2C controller is enabled (IC_ENABLE=1); AND I2C controller is NOT engaged in any Master (TX, RX) operation (IC_STATUS[5]=0); AND I2C controller is enabled to operate in Master mode (IC_CON[0]=1); AND there are no entries in the TX FIFO (IC_STATUS[2]=1) †