Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

3.2. Clock Manager Block Diagram and System Integration

Figure 4. Clock Manager Block Diagram
Table 10.  Arria 10 Top Level Clocks
Clock Name Source/Destination Description
mpu_free_clk Clock manager To MPU complex Source clock from clock manager for both MPU clock groups.
mpu_clk Internal to MPU complex MPU main clock
mpu_l2ram_clk Internal to MPU complex and HMC switch in NOC. MPU L2 RAM clock and HMC switch in NOC. Fixed at ½ mpu_clk.
mpu_periph_clk Internal to MPU complex MPU peripherals clock for interrupts, timers, and watchdogs. Fixed at ¼ mpu_clk.
l3_main_free_clk Clock manager to NOC/Peripherals Interconnect L3 main switch clock. Always free running.
l4_sys_free_clk Clock manager to NOC/Peripherals Interconnect L4 system clock. Always free running.
l4_main_clk Clock manager to NOC/Peripherals L4 Interconnect clock for fast peripherals including DMA, SPIM, SPIS and TCM.
l4_mp_clk Clock manager to NOC/Peripherals Interconnect L4 peripheral clock.
l4_sp_clk Clock manager to NOC/Peripherals Interconnect L4 slow peripheral clock.
cs_at_clk Clock manager to CoreSight* /NOC CoreSight* Trace clock and debug time stamp clock.
cs_pdbg_clk Clock manager to CoreSight* CoreSight* bus clock
cs_trace_clk Clock manager to CoreSight*

CoreSight* Trace I/O clock. This is independent and defaults to a low frequency (25 MHz) for lower speed debuggers.

Not required to be sync. to other clocks (but keep in clock group as hardware managed)

cs_timer_clk Clock manager to CoreSight* /NOC

CoreSight* timer clock. Same as cs_at_clk with different software enable to ensure MPU clock running.

Not required to be sync. to other clocks (but still hardware managed).

fpga2soc_clk FPGA fabric to NOC FPGA to SoC interface clock from the FPGA.
soc2fpga_clk FPGA fabric to NOC SoC to FPGA interface clock from the FPGA.
lws2f_clk FPGA fabric to NOC LWHPS to FPGA interface clock from FPGA.
hmc_free_clk From HMC to HMC switch in NOC HMC interface clock from HMC (Hard Memory Controller) in FPGA.

f2h_sdram0_clk

f2s_sdram1_clk

f2h_sdram2_clk

FPGA fabric to HMC switch in NOC FPGA fabric SDRAM write interfaces clocks.
f2h_pclkdbg FPGA fabric to CoreSight* bridge CoreSight* FPGA fabric APB* debug port clock
usb[0,1]_ulpi_clk I/O to USB ULPI clock for PHY.