Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

29.2.2. User Clocks

A user clock is a PLL output that is connected to the FPGA fabric rather than the HPS. You can connect a user clock to logic that you instantiate in the FPGA fabric.

  • h2f_user0_clock—HPS-to_FPGA user clock, driven from main PLL
  • h2f_user1_clock—HPS-to-FPGA user clock, driven from peripheral PLL