Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

28.4.1. Configuring Peripherals

The Pin MUX and Peripherals tab contains three sub tabs IP Selection, Advanced Pin Placement, and Advanced FPGA Placement. The IP Selection tab contains a list of peripherals that can be enabled and either routed to the HPS I/Os or to the FPGA. You can enable one or more instances of each peripheral type by using the drop down menu next to each peripheral. When enabled, some peripherals also have mode settings specific to their functions.

Note: Once you have selected a peripheral, you must click the Apply Selections button in order to enable the selected peripherals.
Under the the IP Selection tab, Platform Designer (Standard) allows you to boot from the following flash device sources if selected.
  • NAND
  • SD/MMC
  • QSPI

In the Advanced Pin Placement tab you can be more specific about the placement of each peripheral in the HPS dedicated I/O and HPS shared I/O quadrant space. Each location has a pull down IP selection menu where you can select a peripheral for the location.

Pin placement for peripherals cannot span both dedicated I/O and HPS shared I/O, except for the following situations:
  • QSPI signals qspi_ss_o[2] and qspi_ss_o[3] are available to the HPS shared I/O and can be routed to any quadrant selected.
  • If the SD/MMC signals are routed to the HPS shared I/O, and the SDMMC_PWR_ENA pin is required, then it is only available to the HPS dedicated I/O.
  • If the signals for all three EMACs are routed to the HPS shared I/O, the MDIO signals for all three EMACs can be routed to the HPS dedicated I/Os.
  • If the NAND Flash Controller pins are routed to the HPS dedicated I/O, NAND_WP_N is only available to the HPS shared I/O.

In addition, peripheral pins cannot span multiple quadrants within the HPS shared I/O. All pins of an instance must be self-contained in one quadrant, except for NANDx16 and the GPIO modules because of the number of pins required for these peripherals. For example, NANDx16 may be routed to either quadrant 1 and quadrant 2 or quadrant 3 and quadrant 4.

The Advanced FPGA Placement tab allows you to route peripherals to the FPGA. Aside from the IP Selection tab this tab allows you to focus on the FPGA routing only. There are also SDMMC and NAND Bit-width options. You can select the EMAC interface and PHY options on this tab if peripheral is selected.

Note: Changes in the IP Selection tab carry over to the Advanced Pin Placement tab, Advanced FPGA Placement tab, and vise versa.

You can enable the following types of peripherals: