Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

5.2. FPGA Manager Block Diagram and System Integration

Figure 14. FPGA Manager Block Diagram

The FPGA Manager consists of the following blocks:

  • Configuration Data Interface - Accepts and transfers the configuration and decryption data to the FPGA configuration sub system (CSS)
  • Register Slave Interface - Accesses the control and status registers in the FPGA Manager
  • CSS Control - Controls full and partial configuration of the FPGA
  • CSS Monitor - Monitors the status of the FPGA during a full or partial configuration of the device
  • Error Message Register (EMR) Interface - Error message extraction, in case of CRC errors in the FPGA
  • General Purpose I/O Interface - Receives and drives 32 bits of general purpose I/O to and from the FPGA
  • Miscellaneous Core Input Interface - Receives control input signals from the FPGA to support booting the HPS from the FPGA