Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

13.1.3. Functional Description of the On-Chip RAM

The on-chip RAM uses a 64-bit slave interface. The slave interface supports transfers between memory and the L3 interconnect. All reads and writes are serviced in order.

The on-chip RAM has an exclusive monitor, as well. To ensure mutually exclusive access to shared data, use the exclusive access support built into the on-chip RAM. The on-chip RAM contains five monitors. Each monitor can be used by any of the following:
  • CPU and CPU1
  • FPGA2SOC
  • FPGA2SDRAM0
  • FPGA2SDRAM1
  • FPGA2SDRAM2
Note: The on-chip RAM exclusive monitor for the MPU does not differentiate between individual CPUs.