Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

20.4.5.3. Glue Logic for Master Port ss_in_n

When configured as a master, the SPI has an input, ssi_in_n, which can be used by the deciding logic in a multi-master system to disable one master when another has priority. The polarity of this signal depends on the serial protocol in use, and the protocol is dynamically selectable.

The table below lists the three protocols and the effect of ss_in_n on the ability of the master to transfer data. Note that for the SSP protocol the effect of ss_in_n is inverted with respect to the other protocols.

Protocol ss_in_n value Effect on Serial Transfer
Motorola SPI 1 Enabled
0 Disabled
National Semiconductor Microwire 1 Enabled
0 Disabled
Texas Instruments Serial Protocol (SSP) 1 Disabled
0 Enabled
Figure 108. Arbitration Between Multiple Serial Masters
Figure 109. SPI Configured as Master Device