Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

4.2.1.1. Cold Reset Assertion Sequence

The following list describes the assertion steps for cold reset shown in the Cold Reset timing diagram:

  1. Assert all module resets.
  2. Wait for level cold reset requests to de-assert
  3. Wait for 32 cycles, de-asserts clock manager cold reset
  4. Wait the nRST count (default is 2048). De-assert NRST Output Enable.
  5. Wait 256 clocks to allow the nRST pin to stabilize. Start sampling nRST input pin.

  6. Wait for level warm reset requests to all de-assert.

  7. Go to de-assertion sequence.