Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

29.5.1.3. Quad SPI Flash Controller Interface

Table 242.  Quad SPI Flash Controller Platform Designer (Standard) Port Mappings
Platform Designer (Standard) Port Name Routed to FPGA Routed to HPS I/O HPS Pin Name
qspi_sclk_out Yes Yes QSPI_CLK
qspi_s2f_clk Yes No -
qspi_io0_i Yes Yes QSPI_IO0
qspi_io0_o Yes Yes
qspi_mo_oe0 Yes Yes
qspi_io1_i Yes Yes QSPI_IO1
qspi_io1_o Yes Yes
qspi_mo_oe1 Yes Yes
qspi_io2_i Yes Yes QSPI_IO2_WPN
qspi_io2_wpn_o Yes Yes
qspi_mo_oe2 Yes Yes
qspi_io3_i Yes Yes QSPI_IO3_HOLD
qspi_io3_hold_o Yes Yes
qspi_mo_oe3 Yes Yes
qspi_ss_o[3:0] Yes Yes QSPI_SS[3:0]