Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

24.2. Timer Block Diagram and System Integration

Each timer includes a slave interface for control and status register (CSR) access, a register block, and a programmable 32‑bit down counter that generates interrupts on reaching zero. The timer operates on a single clock domain driven by the clock manager.
Figure 150. Timer Block Diagram