Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

17.1. Features of the DMA Controller

The HPS provides one DMAC to handle the data transfer between memory-mapped peripherals and memories, off-loading this work from the MPU subsystem.

  • The DMAC supports multiple transfer types:
    • Memory-to-memory
    • Memory-to-peripheral
    • Peripheral-to-memory
    • Scatter-gather
  • Supports up to eight DMA channels
  • Supports up to eight outstanding AXI* read and eight outstanding AXI* write transactions
  • Supports scheduling up to 16 outstanding read and 16 outstanding write instructions
  • Supports nine interrupt lines into the MPU subsystem:
    • One for DMA thread abort
    • Eight for events
  • Supports 32 peripheral request interfaces:
    • Eight for FPGA
      • FPGA 5 is multiplexed with Security Manager TX
      • FPGA 6 is multiplexed with I2C_EMAC2_TX
      • FPGA 7 is multiplexed with I2C_EMAC2_RX
    • Five for I2C
    • Three for I2C (EMAC)
    • Eight for SPI
    • Two for quad SPI
    • One for System Trace Macrocell
    • Four for UART
    • One for FPGA manager
The DMA controller provides:
  • An instruction processing block that enables it to process program code that controls a DMA transfer
  • An Arm* Advanced Microcontroller Bus Architecture ( AMBA* ) Advanced eXtensible Interface ( AXI* ) master interface unit to fetch the program code from system memory into its instruction cache
    Note: The AXI* master interface is used to perform DMA data transfer as well. The DMA instruction execution engine executes the program code from its instruction cache and schedules read or write AXI* instructions through the respective instruction queues.
  • A multi-FIFO (MFIFO) data buffer that it uses to store data that it reads, or writes, during a DMA transfer
  • Nine interrupt outputs to enable efficient communication of events to the MPU interrupt controller
    Note: The peripheral request interfaces support the connection of DMA-capable peripherals to enable memory-to-peripheral and peripheral-to-memory transfers to occur, without intervention from the processor. Since the HPS supports some peripherals that do not comply with Arm* DMA peripheral interface protocol, adapters are added to allow these peripherals to work with the DMAC.

The following peripheral interface protocols are supported:

  • Synopsys protocol
    • FPGA manager
    • Serial peripheral interface (SPI)
    • Universal asynchronous receiver transmitter (UART)
    • Inter-integrated circuit (I2C)
    • FPGA
  • Arm* protocol
    • Quad SPI flash controller
    • System trace macrocell (STM)

Dual slave interfaces enable the operation of the DMA controller to be partitioned into a secure and non-secure state. The network interconnect must be configured to ensure that only secure transactions can access the secure interface. The slave interfaces can access status registers and also be used to directly issue and execute instructions in the DMA controller.

The DMAC has the following features:
  • A small instruction set that provides a flexible method of specifying the DMA operations. This architecture provides greater flexibility than the fixed capabilities of a Linked-List Item (LLI) based DMA controller