Arria® 10 Hard Processor System Technical Reference Manual
ID
683711
Date
5/09/2025
Public
1. Arria® 10 Hard Processor System Technical Reference Manual Revision History
2. Introduction to the Hard Processor System
3. Clock Manager
4. Reset Manager
5. FPGA Manager
6. System Manager
7. SoC Security
8. System Interconnect
9. HPS-FPGA Bridges
10. Cortex*-A9 Microprocessor Unit Subsystem
11. CoreSight* Debug and Trace
12. Error Checking and Correction Controller
13. On-Chip Memory
14. NAND Flash Controller
15. SD/MMC Controller
16. Quad SPI Flash Controller
17. DMA Controller
18. Ethernet Media Access Controller
19. USB 2.0 OTG Controller
20. SPI Controller
21. I2C Controller
22. UART Controller
23. General-Purpose I/O Interface
24. Timer
25. Watchdog Timer
26. Hard Processor System I/O Pin Multiplexing
27. Introduction to the HPS Component
28. Instantiating the HPS Component
29. HPS Component Interfaces
30. Simulating the HPS Component
A. Booting and Configuration
8.1.1. Features of the System Interconnect
8.1.2. System Interconnect Block Diagram and System Integration
8.1.3. Arria 10 HPS Secure Firewalls
8.1.4. About the Rate Adapters
8.1.5. About the SDRAM L3 Interconnect
8.1.6. About Arbitration and Quality of Service
8.1.7. About the Service Network
8.1.8. About the Observation Network
8.2.1. System Interconnect Address Spaces
8.2.2. Secure Transaction Protection
8.2.3. System Interconnect Master Properties
8.2.4. System Interconnect Slave Properties
8.2.5. System Interconnect Clocks
8.2.6. System Interconnect Resets
8.2.7. Functional Description of the Rate Adapters
8.2.8. Functional Description of the Firewalls
8.2.9. Functional Description of the SDRAM L3 Interconnect
8.2.10. Functional Description of the Arbitration Logic
8.2.11. Functional Description of the QoS Generators
8.2.12. Functional Description of the Observation Network
10.3.1. Functional Description
10.3.2. Implementation Details
10.3.3. Cortex*-A9 Processor
10.3.4. Interactive Debugging Features
10.3.5. L1 Caches
10.3.6. Preload Engine
10.3.7. Floating Point Unit
10.3.8. NEON* Multimedia Processing Engine
10.3.9. Memory Management Unit
10.3.10. Performance Monitoring Unit
10.3.11. Arm* Cortex* -A9 MPCore Timers
10.3.12. Generic Interrupt Controller
10.3.13. Global Timer
10.3.14. Snoop Control Unit
10.3.15. Accelerator Coherency Port
11.1. Features of CoreSight* Debug and Trace
11.2. Arm* CoreSight* Documentation
11.3. CoreSight Debug and Trace Block Diagram and System Integration
11.4. Functional Description of CoreSight Debug and Trace
11.5. CoreSight* Debug and Trace Programming Model
11.6. CoreSight Debug and Trace Address Map and Register Definitions
11.4.1. Debug Access Port
11.4.2. System Trace Macrocell
11.4.3. Trace Funnel
11.4.4. CoreSight Trace Memory Controller
11.4.5. AMBA* Trace Bus Replicator
11.4.6. Trace Port Interface Unit
11.4.7. Embedded Cross Trigger System
11.4.8. Program Trace Macrocell
11.4.9. HPS Debug APB* Interface
11.4.10. FPGA Interface
11.4.11. Debug Clocks
11.4.12. Debug Resets
14.1. NAND Flash Controller Features
14.2. NAND Flash Controller Block Diagram and System Integration
14.3. NAND Flash Controller Signal Descriptions
14.4. Functional Description of the NAND Flash Controller
14.5. NAND Flash Controller Programming Model
14.6. NAND Flash Controller Address Map and Register Definitions
15.1. Features of the SD/MMC Controller
15.2. SD/MMC Controller Block Diagram and System Integration
15.3. SD/MMC Controller Signal Description
15.4. Functional Description of the SD/MMC Controller
15.5. SD/MMC Controller Programming Model
15.6. SD/MMC Controller Address Map and Register Definitions
16.1. Features of the Quad SPI Flash Controller
16.2. Quad SPI Flash Controller Block Diagram and System Integration
16.3. Quad SPI Flash Controller Signal Description
16.4. Functional Description of the Quad SPI Flash Controller
16.5. Quad SPI Flash Controller Programming Model
16.6. Quad SPI Flash Controller Address Map and Register Definitions
16.4.1. Overview
16.4.2. Data Slave Interface
16.4.3. SPI Legacy Mode
16.4.4. Register Slave Interface
16.4.5. Local Memory Buffer
16.4.6. DMA Peripheral Request Controller
16.4.7. Arbitration between Direct/Indirect Access Controller and STIG
16.4.8. Configuring the Flash Device
16.4.9. XIP Mode
16.4.10. Write Protection
16.4.11. Data Slave Sequential Access Detection
16.4.12. Clocks
16.4.13. Resets
16.4.14. Interrupts
18.6.1. System Level EMAC Configuration Registers
18.6.2. EMAC FPGA Interface Initialization
18.6.3. EMAC HPS Interface Initialization
18.6.4. DMA Initialization
18.6.5. EMAC Initialization and Configuration
18.6.6. Performing Normal Receive and Transmit Operation
18.6.7. Stopping and Starting Transmission
18.6.8. Programming Guidelines for Energy Efficient Ethernet
18.6.9. Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output
19.1. Features of the USB OTG Controller
19.2. USB OTG Controller Block Diagram and System Integration
19.3. USB 2.0 ULPI PHY Signal Description
19.4. Functional Description of the USB OTG Controller
19.5. USB OTG Controller Programming Model
19.6. USB 2.0 OTG Controller Address Map and Register Definitions
29.5.1.1. NAND Flash Controller Interface
29.5.1.2. SD/MMC Controller Interface
29.5.1.3. Quad SPI Flash Controller Interface
29.5.1.4. Ethernet Media Access Controller Interface
29.5.1.5. USB 2.0 OTG Controller Interface
29.5.1.6. SPI Controller Interface
29.5.1.7. I2C Controller Interface
29.5.1.8. UART Interface
30.1. Simulation Flows
30.2. Clock and Reset Interfaces
30.3. FPGA-to-HPS AXI Slave Interface
30.4. HPS-to-FPGA AXI Master Interface
30.5. Lightweight HPS-to-FPGA AXI Master Interface
30.6. HPS-to-FPGA MPU Event Interface
30.7. Interrupts Interface
30.8. HPS-to-FPGA Debug APB* Interface
30.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface
30.10. HPS-to-FPGA Cross-Trigger Interface
30.11. FPGA-to-HPS DMA Handshake Interface
30.12. Boot from FPGA Interface
30.13. Security Manager Anti-Tamper Signals Interface
30.14. EMIF Conduit
30.15. Pin MUX and Peripherals
17.1. Features of the DMA Controller
The HPS provides one DMAC to handle the data transfer between memory-mapped peripherals and memories, off-loading this work from the MPU subsystem.
- The DMAC supports multiple transfer types:
- Memory-to-memory
- Memory-to-peripheral
- Peripheral-to-memory
- Scatter-gather
- Supports up to eight DMA channels
- Supports up to eight outstanding AXI* read and eight outstanding AXI* write transactions
- Supports scheduling up to 16 outstanding read and 16 outstanding write instructions
- Supports nine interrupt lines into the MPU subsystem:
- One for DMA thread abort
- Eight for events
- Supports 32 peripheral request interfaces:
- Eight for FPGA
- FPGA 5 is multiplexed with Security Manager TX
- FPGA 6 is multiplexed with I2C_EMAC2_TX
- FPGA 7 is multiplexed with I2C_EMAC2_RX
- Five for I2C
- Three for I2C (EMAC)
- Eight for SPI
- Two for quad SPI
- One for System Trace Macrocell
- Four for UART
- One for FPGA manager
- Eight for FPGA
The DMA controller provides:
- An instruction processing block that enables it to process program code that controls a DMA transfer
- An Arm* Advanced Microcontroller Bus Architecture ( AMBA* ) Advanced eXtensible Interface ( AXI* ) master interface unit to fetch the program code from system memory into its instruction cache
Note: The AXI* master interface is used to perform DMA data transfer as well. The DMA instruction execution engine executes the program code from its instruction cache and schedules read or write AXI* instructions through the respective instruction queues.
- A multi-FIFO (MFIFO) data buffer that it uses to store data that it reads, or writes, during a DMA transfer
- Nine interrupt outputs to enable efficient communication of events to the MPU interrupt controller
Note: The peripheral request interfaces support the connection of DMA-capable peripherals to enable memory-to-peripheral and peripheral-to-memory transfers to occur, without intervention from the processor. Since the HPS supports some peripherals that do not comply with Arm* DMA peripheral interface protocol, adapters are added to allow these peripherals to work with the DMAC.
The following peripheral interface protocols are supported:
- Synopsys protocol
- FPGA manager
- Serial peripheral interface (SPI)
- Universal asynchronous receiver transmitter (UART)
- Inter-integrated circuit (I2C)
- FPGA
- Arm* protocol
- Quad SPI flash controller
- System trace macrocell (STM)
Dual slave interfaces enable the operation of the DMA controller to be partitioned into a secure and non-secure state. The network interconnect must be configured to ensure that only secure transactions can access the secure interface. The slave interfaces can access status registers and also be used to directly issue and execute instructions in the DMA controller.
The DMAC has the following features:
- A small instruction set that provides a flexible method of specifying the DMA operations. This architecture provides greater flexibility than the fixed capabilities of a Linked-List Item (LLI) based DMA controller