Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

8.2.3. System Interconnect Master Properties

The system interconnect connects to slave interfaces through the main L3 interconnect and SDRAM L3 interconnect.

Table 48.  System Interconnect Master Interfaces
Master Interface Width Clock Security SCR11 Access Privilege Issuance (Read/Write/Total) Type
MPU Subsystem L2 cache M0/1 64 mpu_l2ram_clk Per Transaction Yes Transaction based 7/12/23 AXI*
FPGA-to-HPS Bridge 12 32/64/128 fpga2hps_clk Per Transaction Yes Transaction based 8/8/8 AXI*
FPGA-to-SDRAM Ports 12 32/64/128 f2h_sdram_clk[2:0] Per Transaction No Transaction based 8/8/8 AXI*
DMA 64 l4_main_clk Per Transaction No User mode 8/8/8 AXI*
EMAC 0/1/2 32 l4_mp_clk Secure/Non-Secure No User mode 16/16/32 AXI*
USB OTG 0/1 32 l4_mp_clk Nonsecure No User mode 2/2/4 AHB*
NAND 32 l4_mp_clk Nonsecure No User mode 1/1/2 AXI*
SD/MMC 32 l4_mp_clk Nonsecure No User mode 2/2/4 AHB*
ETR 32 cs_at_clk Per Transaction No Transaction based 32/1/32 AXI*
AHB* -AP 32 l4_mp_clk Per Transaction Yes Transaction based 1/1/1 AHB*
11 Security control register (SCR)
12 Ensure that Avalon-MM burst transactions into the HPS do not cross the 4 KB address boundary restriction specified by the AXI* protocol.