Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

7.1.3.5. Clock Configuration

Security Manager is driven by an internal oscillator, cb_intosc_hs_clk, in the Configuration Subsystem. This clock has wide variation across process and temperature. Once the Security Manager reads the fuse information, it drives the boot clock configuration to the Clock Manager. The Clock Manager samples the clock configuration on a cold and warm reset. If the hps_clk_f fuse is blown, the internal oscillator divided by 2, cb_intosc_hs_div2_clk, is used as the boot clock. If the fuse is not blown, an external oscillator is used. During boot ROM execution, the boot code configures the device clock based on the CSEL fuse settings or software code. The cb_intosc_hs_div2_clk can be considered the secure reference clock option.

The CSEL fuse settings have different meanings depending on how the hps_clk_f fuse is configured. When the hps_clk_f fuse is not blown, the external oscillator is the boot clock input.

Table 32.  CSEL Encodings for hps_clk_f = 0

CSEL[3:0] Fuse Value

Description

MPU Clock Value
0x0 When no fuses are blown, the boot ROM returns clocks back to their default (bypass) boot mode and the CPU is driven by the external oscillator (HPS_CLK1), which must be in the range of 10 to 50 MHz. No PLL is enabled. External Oscillator, HPS_CLK1 (10 to 50 MHz)
0x1

This encoding is typically used during a warm reset if you have already configured your clocks or PLL in the clock manager and would like to continue to use this configuration. If this is encoding is selected, no changes are made to these settings and the clock configuration is essentially user selected.

If this is encoding is used during a power-on reset, then whatever the default reset values of the clocks are used.

User-selected clock source. Refer to the Clock Manager chapter for clock register settings.
0x2 Reserved External Oscillator, HPS_CLK1 (10 to 50 MHz)
0x3 Reserved External Oscillator, HPS_CLK1 (10 to 50 MHz)
0x4 Reserved External Oscillator, HPS_CLK1 (10 to 50 MHz)
0x5 Reserved External Oscillator, HPS_CLK1 (10 to 50 MHz)
0x6 Reserved External Oscillator, HPS_CLK1 (10 to 50 MHz)
0x7 External oscillator input clock, HPS_CLK1, is in the range of 10 to 15 MHz 533 to 800Mhz
0x8 External oscillator input clock, HPS_CLK1, is in the range 15 to 20 MHz. 600 to 800Mhz
0x9 External oscillator input clock, HPS_CLK1, is in the range 20 to 25 MHz. 640 to 800Mhz
0xA External oscillator input clock, HPS_CLK1, is in the range 25 to 30 MHz. 666 to 800Mhz
0xB External oscillator input clock, HPS_CLK1, is in the range 30 to 35 MHz. 685 to 800Mhz
0xC External oscillator input clock, HPS_CLK1, is in the range 35 to 40 MHz. 700 to 800Mhz
0xD External oscillator input clock, HPS_CLK1, is in the range 40 to 45 MHz. 711 to 800Mhz
0xE External oscillator input clock, HPS_CLK1, is in the range 45 to 50 MHz. 720 to 800Mhz
0xF The boot ROM returns clocks back to their default (bypass) boot mode and the CPU is driven by the external oscillator (HPS_CLK1). No PLL is enabled. External Oscillator, HPS_CLK1 (10 to 50 MHz)
Table 33.  CSEL Encodings for hps_clk_f = 1

CSEL[3:0] Fuse Value

Description

MPU Clock Value
0x0 Bypass mode; in this mode all clocks are reset and boot mode is ensured active; cb_intosc_hs_div2_clk (cb_intosc_hs clock divided by 2) is used. cb_intosc_hs_div2_clk (60 to 200 MHz)
0x1

This encoding is typically used during a warm reset if you have already configured your clocks or PLL in the Clock Manager and would like to continue to use this configuration. If this is encoding is selected, no changes are made to these settings and the clock configuration is essentially user selected.

If this is encoding is used during a power-on reset, then whatever the default reset values of the clocks are used.

User-selected clock source. Refer to the Clock Manager chapter for clock register settings.
0x2 PLL is used with the internal oscillator (30 to 100 MHz) 120 to 800 MHz
0x3 Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0x4 Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0x5 Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0x6 Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0x7 Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0x8 Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0x9 Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0xA Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0xB Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0xC Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0xD Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0xE Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0xF Bypass mode; reset all clocks and ensure boot mode is active; cb_intosc_hs_div2_clk is used. cb_intosc_hs_div2_clk (60 to 200 MHz)

For more information regarding the CSEL encodings and descriptions, please refer to the Booting and Configuration Appendix.