Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

16.3. Quad SPI Flash Controller Signal Description

The quad SPI controller provides four chip select outputs to allow control of up to four external quad SPI flash devices. The outputs serve different purposes depending on whether the device is used in single, dual, or quad operation mode. The following table lists the I/O pin use of the quad SPI controller interface signals for each operation mode. For more information on which signals are available to the FPGA and HPS I/O, refer to the HPS Component Interfaces chapter.

Table 173.  Interface Pins
Signal Pin Mode Direction Function

qspi_io0_i

qspi_io0_o

qspi_mo_oe[0]

IO0

Single

Output

Data output 0

Dual or quad

Bidirectional

Data I/O 0

qspi_io1_i

qspi_io1_o

qspi_mo_oe[1]

IO1

Single

Input

Data input 0

Dual or quad

Bidirectional

Data I/O 1

qspi_io2_i

qspi_io2_wpn_o

qspi_mo_oe[2]

IO2_WPN

Single or dual

Output

Active low write protect

Quad

Bidirectional

Data I/O 2

qspi_io3_i

qspi_io3_hold_o

qspi_mo_oe[3]

IO3_HOLD

Single, dual, or quad

Bidirectional

Data I/O 3

qspi_ss_o[0] SS0

Single, dual, or quad

Output

Active low slave select 0

qspi_ss_o[1] SS1

Active low slave select 1

qspi_ss_o[2] SS2

Active low slave select 2

qspi_ss_o[3] SS3

Active low slave select 3

qspi_sclk_out

CLK

Single

Output

QSPI serial clock output which connects to the FPGA core fabric

qspi_s2f_clk

QSPI serial clock output which connects to the FPGA clock network

Note: Use the qspi_s2f_clk as the serial clock output to an external SPI device.