Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

10.3.15.4.1. Configuring AxCACHE[3:0] Sideband Signals for Coherent Accesses

The following list highlights how to correctly derive and apply the correct AxCACHE settings for coherent accesses.
  • The correct AxCACHE[3:0] setting is dependent on the MMU page table settings. However, for coherent accesses, AxCACHE[1] must be set to 0x1.
  • For HPS masters, AxCACHE[3:0] is static and applied to the relevant master port through the System Manager.
  • For FPGA masters, AxCACHE[3:0] is applied in the FPGA fabric and can be set for each access.