Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

A.6.3. HPS State on Entry to the Second-Stage Boot Loader

When the boot ROM code is ready to pass control to the second-stage boot loader, the processor (CPU0) is in the following state:

  • Instruction cache is enabled
  • Branch predictor is enabled
  • Data cache is disabled
  • MMU is disabled
  • Floating point unit is enabled
  • NEON vector unit is enabled
  • Processor is in Arm* secure supervisor mode

The boot ROM code sets the Arm* Cortex*-A9 MPCore* registers to the following values:

  • r0—contains the pointer to the shared memory block, which is used to pass information from the boot ROM code to the second-stage boot loader. The shared memory block is located in the top 4 KB of on-chip RAM.
  • r1—contains the length of the shared memory.
  • r2—unused and set to 0x0.
  • r3—points to the version block.

All other MPCore registers are undefined.

Note: When booting CPU0 using the FPGA boot, or when booting CPU1 using any boot source, all MPCore registers, caches, the MMU, the floating point unit, and the NEON vector unit are undefined. HPS subsystems and the PLLs are undefined.

When the boot ROM code passes control to the second-stage boot loader, the following conditions also exist:

  • CPU0 is in a secure system mode.
  • The boot ROM is still mapped to address 0x0.
  • The L4 watchdog 0 timer is active and has been toggled.
  • The shared L2 cache is left in an uninitialized state.

The boot ROM also saves the state of the reset cause in the stat register of the Reset Manager, and this information is available for the Second-Stage Boot Loader to read.