Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

9.1. Features of the HPS-FPGA Bridges

The HPS-FPGA bridges allow masters in the FPGA fabric to communicate with slaves in the HPS logic and vice versa. For example, if you implement memories or peripherals in the FPGA fabric, HPS components such as the MPU can access them. Components implemented in the FPGA fabric, such as the Nios® II processor, can also access memories and peripherals in the HPS logic.
Table 67.   HPS-FPGA Bridge Features

Feature

FPGA-to-HPS Bridge

HPS-to-FPGA Bridge

Lightweight HPS-to-FPGA Bridge

Supports the AMBA* AXI3 interface and FlexNoC low latency interface protocols

Y Y Y

Implements clock crossing and manages the transfer of data across the clock domains in the HPS logic and the FPGA fabric

Y Y Y

Performs data width conversion between the HPS logic and the FPGA fabric

Y Y Y

Allows configuration of FPGA interface widths at instantiation time

Y Y N

Each bridge consists of a master-slave pair with one interface exposed to the FPGA fabric and the other exposed to the HPS logic. The FPGA-to-HPS bridge exposes an AXI* slave interface that you can connect to AXI* or Avalon-MM master interfaces in the FPGA fabric. The HPS-to-FPGA and lightweight HPS-to-FPGA bridges expose an AXI* master interface that you can connect to AXI* or Avalon-MM slave interfaces in the FPGA fabric.