Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

29.5.1.6. SPI Controller Interface

Table 245.  SPI Controller Interface Platform Designer (Standard) Port Mappings
Platform Designer (Standard) Port Name Routed to FPGA Routed to HPS I/O HPS Pin Name
spim0_sclk_out Yes Yes SPIM0_CLK
spim0_mosi_o Yes Yes SPIM0_MOSI
spim0_mosi_oe Yes No
spim0_miso_i Yes Yes SPIM0_MISO
spim0_ss_in_n Yes No -
spim0_mosi_oe Yes No -
spim0_ss0_n_o Yes Yes SPIM0_SS0_N
spim0_ss1_n_o Yes Yes SPIM0_SS1_N
spim0_ss2_n_o Yes No -
spim0_ss3_n_o Yes No -
spim1_sclk_out Yes Yes SPIM1_CLK
spim1_mosi_o Yes Yes SPIM1_MOSI
spim1_mosi_oe Yes Yes
spim1_miso_i Yes Yes SPIM1_MISO
spim1_ss_in_n Yes No -
spim1_ss0_n_o Yes Yes SPIM1_SS0_N
spim1_ss1_n_o Yes Yes SPIM1_SS1_N
spim1_ss2_n_o Yes No -
spim1_ss3_n_o Yes No -
spis0_sclk_in Yes Yes SPIS0_CLK
spis0_mosi_i Yes Yes SPIS0_MOSI
spis0_ss_in_n Yes Yes SPIS0_SS0_N
spis0_miso_o Yes Yes SPIS0_MISO
spis0_miso_oe Yes Yes
spis1_sclk_in Yes Yes SPIS1_CLK
spis1_mosi_i Yes Yes SPIS1_MOSI
spis1_ss_in_n Yes Yes SPIS1_SS0_N
spis1_miso_o Yes Yes SPIS1_MISO
spis1_miso_oe Yes Yes