Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

30.15.2. HPS Conduit Interfaces Connecting to the FPGA

When connecting to the FPGA, the Pin Mux and Peripherals interface is indicative to the peripheral name and represented in the "Conduit" column in the following table. The following tables for each of the peripherals, lists the conduits and their interfaces. In order to see the signals, you must select "Show Signals".

Table 291.  SD/MMC Interface Simulation Model
To FPGA Conduit Interface(s)
1 sdmmc

sdmmc_reset

sdmmc_clk

Table 292.  EMAC Pins Interface Simulation Model
To FPGA Conduit Interface(s)
1

emac0

i2cemac0 — when PHY Options is set to "I2C"

emac_ptp_ref_clock

emac0_rx_clk_in

emac0_tx_clk_in

emac0_gtx_clk

emac0_tx_reset

emac0_rx_reset

emac0_md_clk — when PHY Options is set to "MDIO"

i2cemac0_scl_in — when PHY Options is set to "I2C"

2

emac1

i2cemac1 — when PHY Options is set to "I2C"

emac_ptp_ref_clock

emac1_rx_clk_in

emac1_tx_clk_in

emac1_gtx_clk

emac1_tx_reset

emac1_rx_reset

emac1_md_clk — when PHY Options is set to "MDIO"

i2cemac1_scl_in — when PHY Options is set to "I2C"

3

emac2

i2cemac2 — when PHY Options is set to "I2C"

emac_ptp_ref_clock

emac2_rx_clk_in

emac2_tx_clk_in

emac2_gtx_clk

emac2_tx_reset

emac2_rx_reset

emac2_md_clk — when PHY Options is set to "MDIO"

i2cemac2_scl_in — when PHY Options is set to "I2C"

Table 293.  SPIM Pins Interface Simulation Model
To FPGA Conduit Interface(s)
1 spim0

spim0_sclk_out

2

spim0

spim1

spim0_sclk_out

spim1_sclk_out

Table 294.  SPIS Pins Interface Simulation Model
To FPGA Conduit Interface(s)
1 spis0

spis0_sclk_out

2

spis0

spis1

spis0_sclk_out

spis1_sclk_out

Table 295.  UART Pins Interface Simulation Model
To FPGA Conduit Interface(s)
1 uart0 None
2

uart0

uart1

Table 296.  I2C Pins Interface Simulation Model
To FPGA Conduit Interface(s)
1 i2c0

i2c0_scl_in

i2c0_clk

2

i2c0

i2c1

i2c0_scl_in

i2c0_clk

i2c1_scl_in

i2c1_clk

Table 297.  NAND Pins Interface Simulation Model
To FPGA Conduit Interface(s)
1 nand None
Table 298.  Trace Pins Interface Simulation Model
To FPGA Conduit Interface(s)
1 trace

trace_s2f_clk

Table 299.  QSPI Pins Interface Simulation Model
To FPGA Conduit Interface(s)
1 qspi None