Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

A.4.4.3.1. Quad SPI Controller Default Settings

Table 319.  Quad SPI Controller Default Settings

Parameter

Default Setting

Register Value

SPI baud rate

Divide by 4

The master mode baud rate divisor field (bauddiv) of the quad SPI configuration register (cfg) in the quad SPI controller registers (qspiregs) = 1.

Read opcode

Refer to the "QSPI Controller Clock Options Based on CSEL and HPS_CLK Fuse Settings" table to determine the correct configuration of the HPS_CLK and CSEL fuses for Normal or Fast Reads.

The read opcode in non-XIP mode field (rdopcode) in the device read instruction register (devrd) = 0x3 (for normal read) and 0xB (for fast read).

Instruction type

Single I/O (1 bit wide)

The address transfer width field (addrwidth) and data transfer width field (datawidth) of the devrd register = 0.

Number of address bytes

3 bytes

The number of address bytes field (numaddrbytes) of the device size register (devsz) = 2.

Note: Before a reset, you must ensure that the QSPI flash device is configured to 3 byte address mode for the boot ROM to function properly.

Delay in terms of l4_main_clk for the length that the master mode chip select outputs are deasserted between words when the clock phase is zero

The default setting in clock cycles must equal 200 ns

The clock delay for chip select deassert (field nss in the quad SPI device delay register (delay)).

Refer to delay[31:24] in the "Quad SPI Flash Delay Configuration" table in the "Quad SPI Flash Delay Configuration" section for calculations.

Delay in terms of l4_main_clk clock cycles between one chip select being deactivated and the activation of another. This delay ensures a quiet period between the selection of two different slaves and requires the transmit FIFO to be empty

The default setting is 0 clock cycles.

The clock delay for chip select deactivation (field btwn in the delay register = 0x0).

Delay in terms of l4_main_clk clock cycles between the last bit of the current transaction and the first bit of the next transaction. If the clock phase is zero, the first bit of the next transaction refers to the cycle in which the chip select is deselected

The default setting in clock cycles must equal 20 ns.

The clock delay for last transaction bit (field after in the delay register).

Refer to delay[15:8] in the "Quad SPI Flash Delay Configuration" table in the "Quad SPI Flash Delay Configuration" section for calculations.

Added delay in terms of l4_main_clk clock cycles between setting qspi_n_ss_out low and first bit transfer

The default setting in clock cycles must equal 20 ns.

The clock delay of qspi_n_ss_out (field init in the delay register).

Refer to delay[7:0] in the "Quad SPI Flash Delay Configuration" table in the "Quad SPI Flash Delay Configuration" section for calculations.