Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

A.4.7. L4 Watchdog 0 Timer

The boot ROM enables the L4 Watchdog 0 Timer early in the boot process.

This watchdog is reserved for the boot ROM until the second-stage boot loader indicates that it has started correctly and taken control of the exception vectors. The timeout is at least one second, depending on the clock select setting. Because the watchdog is reset just before the control passes to second-stage boot loader, the second-stage boot loader must reset the watchdog when it begins execution.

The L4 watchdog 0 timer is reserved for boot ROM use. While booting, if a watchdog reset happens before software control passes to the second-stage boot loader, the boot ROM code attempts to load the last valid second-stage boot loader image, identified by the initswlastld register in the System Manager.

If the watchdog reset happens after the second-stage boot loader has started executing but before it writes a valid value to initswstate register, the boot ROM increments initswlastld and attempts to load that image. If the watchdog reset happens after the second-stage boot loader writes a valid value to initswstate register, the boot ROM code attempts to load the image indicated by initswlastld register.