Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

7.2.2.2.1.1. Secure Transaction Example

A successful secure access attempt by a master, depends on the security bit configuration in the Security Control Register and the value of the master secure flag sent by the master.

All SoC transactions are set to secure out of reset with a return of random data when transactions are blocked. If you want an error response returned for blocked transactions, you must set the error_response bit in the global register of the noc_fw_ddr_l3_ddr_scr module at base address 0xFFD13400. If this bit is clear, transactions blocked by the firewall return random data.

Note: Future devices may not support the return of random data and may only support an error response for blocked firewall transactions. For designs that may be ported to future devices, Intel recommends you to set the error_response bit in the global register.

To initiate a secure transaction:

  1. The master drives the address of the slave as well as the master secure flag signal, indicating that the access is intended to be secure.
  2. The firewall compares the programmed security bit of the master-slave peripheral pair to the master secure flag signal to determine if the access is valid.
  3. If the access is valid, the transaction passes to the next level. If the access is not valid, random data is fed back to the master.
Table 41.  Peripheral and System Transaction Results

Security Bit in Firewall Register

Master Secure Flag

Transaction Pass/Fail Transaction Type

0

0

No None (Blocked transaction)

0

1

Yes Secure

1

0

Yes Non-secure

1

1

Yes Secure