Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

A.7.3. Arria 10 SoC FPGA Configuration Sequence Through FPGA Manager

The FPGA Manager in the HPS has the capability to execute an initial FPGA configuration using the full or early I/O release flow.
The steps below detail the programming of the FPGA Manager to initiate configuration.
  1. Read the f2s_msel[2:0] field in the imgcfg_stat register to verify that the configuration mode is the passive fast (000) or passive slow (001).
  2. Write the cfgwidth bit of the imgcfg_ctrl_02 register in the FPGA manager to match the characteristics of the configuration image. For full, standard configuration, the cfgwidth bit must be set to 1. You can only initiate a full, standard configuration in 32-bit passive parallel mode.
  3. Configure the cdratio field. The cdratio is a function of the datawidth and whether the POF in encrypted or compressed. This information should be provided through the Intel® Quartus® Prime configuration. For example,if cfgwidth is 32-bits and the POF is compressed, you must program the cdratio field to 0x8. If the POF is encrypted, then program the cdratio to 0x4.
  4. Ensure there are no other external devices interfering with the FPGA programming. Poll the f2s_nconfig_pin and f2s_nstatus_pin bits from the imgcfg_stat register until they are both 1.
  5. Program the following bits to deassert signal drives from the HPS before overriding the signals.
    • s2f_nce =1 in the imgcfg_ctrl_01 register
    • s2f_pr_request= 0 in the imgcfg_ctrl_01 register
    • en_cfg_ctrl= 0 in the imgcfg_ctrl_02 register
    • s2_nconfig = 1 in the imgcfg_ctrl_00 register
    • s2f_nstatus_oe = 0 in the imgcfg_ctrl_00 register
    • s2f_condone_oe = 0 imgcfg_ctrl_00 register
  6. Enable overrides for the DATA, DCLK, nCE, PR_REQUEST and nCONFIG signals.
    • s2f_nenable_config = 0 in the imgcfg_ctrl_01 register
    • s2f_nenable_nconfig = 0 in the imgcfg_ctrl_00 register
  7. Disable overrides for the nSTATUS and CONF_DONE signals.
    • s2f_nenable_nstatus = 1 in the imgcfg_ctrl_00 register
    • s2f_nenable_condone = 1 in the imgcfg_ctrl_00 register
  8. Assert the chip select signal.
    • s2f_nce=0 in the imgcfg_ctrl_01 register
  9. Repeat step 4. Ensure there are no other external devices interfering with the FPGA programming. Poll the f2s_nconfig_pin and f2s_nstatus_pin bits from the imgcfg_stat register until they are both 1.
  10. Reset the configuration.
    1. Write a 0 to the s2f_nconfig bit in the imgcfg_ctrl_00 register.
    2. Poll the f2s_nstatus_pin bit in the imgcfg_stat register until it is clear.
    3. Write a 1 to the s2f_nconfig bit in the imgcfg_ctrl_00 register.
    4. Poll the f2s_nstatus_pin bit in the imgcfg_stat register until it is set. In addition, read and confirm the f2s_condone_pin is clear and the f2s_condone_oe is set in the imgcfg_stat register.
  11. Enable DCLK and the DATA path by setting the en_cfg_ctrl bit in the imgcfg_ctrl_02 register.
  12. Write the bitstream data to the img_data_w register. When sending the bitstream data, you can periodically read and confirm that the f2s_nstatus_pin bit is set in the imgcfg_stat register. If it is not set, configuration has failed and you must restart with step 1.
  13. When you have completed writing the data, continuously poll the f2s_condone_pin bit in the imgcfg_stat register until it reads as 1. When this bit is 1, it indicates configuration has completed. If the routine times out with f2s_nstatus_pin=0, configuration has failed and you must restart from step 1.
  14. Write the dclkcnt register with 0xF and continuously poll until the dclkcntstat register reads as 0x0. A minimum of 2 DCLK cycles are needed after the CONFIG_DONE assertion for initialization to start.
  15. Wait for the initialization sequence to complete. Poll the f2s_usermode bit in the imgcfg_stat register until it reads as 1.
  16. Disable the DATA path and DCLK by clearing the en_cfg_ctrl bit in the imgcfg_ctrl_02 register.
  17. Disable the chip select. Set the s2f_nce bit in the imgcfg_ctrl_01 register.
  18. Disable overrides to the nCONFIG, DATA and DCLK signals.
    • s2f_nenable_config=1
    • s2f_nenable_nconfig=1
  19. Check that user mode is enabled and the configuration is done by checking that the bits below have the following values:
    • f2s_usermode=1 in the imgcfg_stat register
    • f2s_nstatus_pin=1 in the imgcfg_stat register
    • f2s_condone_pin=1 in the imgcfg_stat register