Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

16.4.2.2.2. Indirect Write Operation

An indirect write operation programs data from the SRAM to the flash memory. The indirect write operations are controlled by the following registers:

  • Indirect write transfer register (indwr)
  • Indirect write transfer watermark register (indwrwater)
  • Indirect write transfer start address register (indwrstaddr)
  • Indirect write transfer number bytes register (indwrcnt)
  • indaddrtrig register

These registers need to be configured prior to issuing indirect write operations. The start address needs to be defined in the indwrstaddr register and the total number of bytes to be written is specified in the indwrcnt register. The start indirect write bit (start) of the indwr register triggers the indirect write operation from the SRAM to the flash memory.

To write data from the SRAM to the flash device, an external master issues 32-bit write transactions to the data slave. The address of the write access must be in the indirect address range. You can configure the indirect address through the indaddrtrig register. The external master can issue 32-bit writes until the last word of an indirect transfer. On the final write, the external master may issue a 32-bit, 16-bit or 8-bit write to complete the transfer. If there are less than four bytes of data to write on the last transfer, the external master can still issue a 32-bit write and the quad SPI controller discards the extra bytes.

The SRAM size can limit the amount of data that the quad SPI controller can accept from the external master. If the SRAM is not full at the point of the write access, the data is pushed to the SRAM with minimum latency. If the external master attempts to push more data to the SRAM than the SRAM can accept, the quad SPI controller backpressures the external master with wait states. When the SRAM resource is freed up by pushing the data from SRAM to the flash memory, the SRAM is ready to receive more data from the external master. When the SRAM holds an equal or greater number of bytes than the size of a flash page, or when the SRAM holds all the remaining bytes of the current indirect transfer, the quad SPI controller initiates a write operation to the flash memory.

The processor can also use the SRAM fill level, in the sramfill register, to control when to write more data into the SRAM.

Alternatively, you can configure the fill level watermark of the SRAM in the indwrwater register. When the SRAM fill level falls below the watermark level, an indirect transfer watermark interrupt is generated to tell the software to write the next page of data to the SRAM. Because the quad SPI controller initiates non-end-of-data writes to the flash memory only when the SRAM contains a full flash page of data, you must set the watermark level to a value greater than one flash page to avoid the system stalling. You can disable this watermark feature by writing a value of all ones to the indwrwater register.

If the address of the write access is outside the range of the indirect trigger address, one of the following actions occurs:

  • When direct access mode is enabled, the write uses direct access mode.
  • When direct access mode is disabled, the slave returns an error back to the requesting master.

You can cancel an indirect operation by setting the cancel indirect write bit (cancel) of the indwr register to 1. For more information, refer to the “Indirect Write Operation with DMA Disabled” section.