Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

2.2.6.1. NAND Flash Controller

The NAND flash controller is based on the Cadence® Design IP® NAND Flash Memory Controller and offers the following functionality and features:

  • Supports up to four chip selects. One chip select is connected to an HPS I/O pin and the rest can be connected to the FPGA I/O pins.
  • Integrated descriptor-based DMA controller
  • 8-bit and 16-bit ONFI 1.0 NAND flash devices
  • Programmable page sizes of 512 bytes, 2 KB, 4 KB, and 8 KB
  • Supports 32, 64, 128, 256, 384, and 512 pages per block
  • Programmable hardware ECC for single-level cell (SLC) and multi-level cell (MLC) devices
  • 512-byte ECC sector size with 4-, 8-, or 16-bit correction
  • 1 KB ECC sector size with 24-bit correction