Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

10.9. Cortex*-A9 MPU Subsystem Register Implementation

The following configurations are available through registers in the Cortex*-A9 subsystem:

  • All processor‑related controls, including the MMU and L1 caches, are controlled using the Coprocessor 15 (CP15) registers of each individual processor.
  • All SCU registers, including control for the timers and GIC, are memory mapped.
  • All L2 cache registers are memory‑mapped.