Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

9.3.1. Functional Description of the FPGA-to-HPS Bridge

The FPGA-to-HPS bridge provides access to the peripherals in the HPS from the FPGA. This access is available to any master implemented in the FPGA fabric. You can configure the bridge slave, which is exposed to the FPGA fabric, to support the AXI protocol, with a data width of 32, 64 or 128 bits. The FPGA-to-HPS bridge multiplexes the configured data width from the L3 interconnect to the FPGA interface.

Table 68.  FPGA-to-HPS Bridge PropertiesThe following table lists the properties of the FPGA-to-HPS bridge, including the configurable slave interface exposed to the FPGA fabric.
Bridge Property Value

Data width19

32, 64, or 128 bits

Clock domain

fpga2hps_clk (max 400 MHz)

Byte address width

32 bits

ID width

4 bits

Read acceptance

8 transactions

Write acceptance

8 transactions

Total acceptance

16 transactions

The FPGA-to-HPS bridge is configurable in the HPS component parameter editor, available in Platform Designer and the IP Catalog. The HPS component parameter editor allows you to set the data path width and the bridge protocol, according to the FPGA bitstream.

Warning: To avoid memory aliasing issues, ensure that Avalon-MM burst transactions into the HPS do not cross the 4 KB address boundary restriction specified by the AXI protocol.
19 The bridge slave data width is user-configurable at the time you instantiate the HPS component in your system.