Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

8.5.93. trap

Instruction trap
Operation

estatus ←  status

PIE ←  0

U ←  0

ea ←  PC + 4

PC ←  exception handler address

Assembler Syntax

trap

trap imm5

Example

trap

Description

Saves the address of the next instruction in register ea, saves the contents of the status register in estatus, disables interrupts, and transfers execution to the exception handler. The address of the exception handler is specified with the Nios_II Processor parameter editor in Platform Designer.

The 5-bit immediate field imm5 is ignored by the processor, but it can be used by the debugger.

trap with no argument is the same as trap 0.

Usage

To return from the exception handler, execute an eret instruction.

Exceptions

Trap

Instruction Type

R

Instruction Fields

IMM5 = Type of breakpoint

Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0x1d 0x2d
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x2d IMM5 0x3a

Did you find the information on this page useful?

Characters remaining:

Feedback Message