Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Document Table of Contents Region Size or Upper Address Limit

A Platform Designer generation-time option controls whether the amount of memory in the region is defined by size or upper address limit. The size is an integer power of two bytes. The limit is the highest address of the region plus one. The minimum supported region size is 256 bytes but can be configured for larger minimum sizes to save logic resources. The maximum supported region size equals the Nios II address space (a function of the address ranges of slaves connected to the Nios II masters). Any access outside of the Nios II address space is considered not to match any region and triggers an MPU region violation exception.

When regions are defined by size, the size is encoded as a binary mask to facilitate the following MPU region address range matching:

(address & region_mask) == region_base_address

When regions are defined by limit, the limit is encoded as an unsigned integer to facilitate the following MPU region address range matching:

(address >= region_base) && (address < region_limit)

The region limit uses a less-than instead of a less-than-or-equal-to comparison because less-than provides a more efficient implementation. The limit is one bit larger than the address so that full address range may be included in a range. Defining the region by limit results in slower and larger address range match logic than defining by size but allows finer granularity in region sizes.

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